1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a field effect transistor (FET) having a reverse self-aligned structure and a method of fabricating the same.
2. Description of the Related Art
As integration increases, semiconductor devices become smaller requiring low resistivity materials to reduce signal delay. Silicide or metal having significantly low resistivity is frequently applied to lower sheet resistance and contact resistance between a gate and a source/drain. In particular, a self-aligned silicide (salicide) process is often used for selectively forming a low resistivity metal silicide film on only a gate electrode and a source/drain region of a transistor without photolithography.
However, when a gate and an active region become smaller with reduced pattern sizes, resistivity of silicide in a gate line increases during the salicide process as shown in FIG. 1. In an active region, silicide becomes relatively thinner, generating voids by a difference in diffusion speed and a partial stress generated below the spacer formed on the sides of a gate due to a pattern. When a shallow junction is made to reduce a short channel effect due to transistor size reduction, current leakage occurs in a junction layer due to silicide. When the salicide process is performed after a gate line is formed, a defect such as dislocation, is generated on a semiconductor substrate below the edge of a gate thus increasing leakage current. In order to reduce dependence on the gate line size as described above, research has been made into using metal, such as tungsten (W), as a gate formation material.
Accordingly, a need remains for a semiconductor device and a method for fabricating the same that prevents the generation of the above-described defects.